G2 DMA reading

The timing is still off and the output doesn’t seem as clean as I’d like. That hasn’t stopped the DMA from working.

I’m starting to think that the falling edge of the G2 clock is when the data is acquired from the line. Setting the logic analyser to 500MHz, it looks like the FR#, BH#, and BL# signals are going down after the rising edge and before the falling edge. I’ve updated my previous post about the G2 bus to reflect that.

This is what a DMA read looks like from the Broadband Adapter:

Wn refers to each 16-bit word.

AL is the lower address, AH is the upper address.

There’s a section marked with ‘???’ which may be junk data, at least as far as the Broadband Adapter is concerned.

When accessing the DMA area, the addresses should be aligned to a 32-byte boudary. Except the last read, which is indicated with bit 0 being a 1. i.e. if one were to read 64 bytes, the first address may be 0xA1848000, while the second would be 0xA1248021.

Here’s a video showing the DMA in action. After the second IRQ comes in, I enable the DMA transfer for the next IRQ and the 32 bytes are received and printed.