G2 DMA writing

Much like the DMA read, the write follows the same rule of every access address must be 32-byte aligned except for the last one, which is the address plus one.

For the demo, I write a 32-byte buffer over to the target. When the DMA completes, a DMA read occurs from the address just written to, then the write buffer is given a new set of data. The reads are verified.

At the moment, I’ve ignored the delay between the high address and the first transaction. As soon as data is ready, it is read or written, depending on the direction from/to the target. So far, this has not had any negative impact and it may be possible to do this for the other transactions, though I haven’t attempted it.

Now that reads and writes are working (possibly with errors that formal verification will expose), I’m going to attempt to get data from the TF cards I have for testing. Starting with the basic card information (capacity, version, manufacturer, etc.).